Competitions
Open Competitions
- Agilent ADS (Teaching and Research Licenses)
- AP1000 Development Boards
- Nanofabrication
- Carrier Platform for Microfluidics Research
- Flip chip attachment
- Encapsulation
- Hermetic sealing and selective encapsulation
- Vacuum packaging
- LETI Silicon Photonics
For more information on our open competitions or to apply, please visit our Competition Homepage.
Fabrication Deadlines
Request for Manufacturing Resources (RFMR) Deadlines:
- 1003PE EPI-Only InP/GaAs Based Technology; March 31, 2010
- 1004PE EPI-Only InP/GaAs Based Technology; April 30, 2010
- 1001CH 0.8-micron CMOS (DALSA); April 12, 2010
- 1001MH 0.8-micron CMOS plus Bulk Micromachining (DALSA); April 12, 2010
- 1001CJ 0.8-micron CMOS; April 12, 2010
- 1001MJ 0.8-micron CMOS plus Bulk Micromachining; April 12, 2010
- 1001CK 0.8-micron CMOS; April 12, 2010
- 1001MK 0.8-micron CMOS plus Bulk Micromachining; April 12, 2010
- 1003MU PolyMUMPs Surface Micromachining; April 12, 2010
Design Submission Deadlines:
- 1002MU PolyMUMPs; March 31, 2010
- 1002MO SOIMUMPs; April 14, 2010
- 1001PF Silicon on Insulator Technology (IMEC); April 29, 2010
- 1001CS 65-nanometre CMOS (TSMC);
Fabrication procedures and forms.
News and Events
News
- IEEE Winnipeg Millimetre-wave testing at the University of Manitoba; March 10, 2010 More..
Events
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Featured Application Notes
Prepared
by Dr. Mohamed Fahmi and Dr. Raafat R. Mansour, Center for Integrated
RF Engineering (CIRFE), Electrical and Computer Engineering Department,
University of Waterloo; and Dr. Mojgan Daneshmand, Electrical and
Computer Engineering Department, University of Alberta.
Prepared
by Chu Pang (undergraduate student), Geng Liu (undergraduate student),
and Paul Chow (professor), The Edward S. Rogers Department of
Electrical and Computer Engineering, University of Toronto.
Prepared
by Robert Sobot, Ph.D.,P.Eng., Assistant Professor, Department of
Electrical and Computer Engineering, University of Western Ontario.
More...
LETI
Silicon Photonics Fabrication Resource Competition
CMC
Microsystems is evaluating the STANDARD and FLEX silicon photonics fabrication
processes that are available from LETI.
The
STANDARD process features:
-
200mm
silicon-on-insulator wafers with 220nm top silicon film and 2000nm buried oxide
(BOX)
-
Top
silicon film can be either crystalline silicon or low-loss amorphous
(hydrogenated) silicon
-
248nm
and 193nm deep UV lithography, enabling features down to ~120nm
-
Transmission
losses of 3-5 dB/cm for 500nm x 200nm waveguides
-
Two
silicon etch depths:
-
70nm
etch (typically used for fibre coupler gratings)
-
220nm
etch (typically used for waveguides and photonic crystal holes)
-
Predefined
fibre coupler grating masks are available
More
information on this technology can be found here:
http://www.epixfab.eu/technology/leti_std/
The FLEX
process has the above features and the following additional features:
-
220nm
silicon on 2000nm BOX, 400nm silicon on 1000nm BOX, or custom thickness
100-400nm
-
Silicon
and germanium epitaxy, in full film or in cavities
-
Implantation
& annealing of boron and phosphorus
-
Metallization
for large metal contacts (openings larger than 2 microns)
-
Resistive
heaters (new feature on the upcoming shuttle run)
More
information on this technology can be found here:
http://www.epixfab.eu/technology/leti_4_flex/
The
STANDARD process supports a wide range of planar lightwave circuits (PLCs) such
as:
-
2D
photonic crystals
-
waveguides
(photonic crystal or ridge)
-
gratings
for fiber coupling
-
multiplexers
(diffraction or arrayed waveguide)
-
ring
resonators
-
filters
In
addition, the FLEX process enables the integration of some active devices on
the same chip.
Target
applications include optical communications, sensors, and biomedical devices.
Contact
Information
For more
information about this technology, such as die sizes, pricing, layout file
requirements, available CAD tools, and related topics, please contact:
Dan
Deptuck, Staff Scientist, Optoelectronics Engineering
Phone: 613.530.4670 E-mail: deptuck@cmc.ca
Xilinx Training
The Xilinx University Program will be presenting two
Professor Workshops at the University of Toronto that will provide hands-on
training for Embedded Systems Design using Xilinx FPGAs:
- Embedded Design Flow: April 29-30, 2010
- Embedded Linux on MicroBlaze: May 10-11, 2010
Registration is free and spaces are limited. Course
details and registration can be accessed at the Xilinx University Program web
site (individuals must be members of the XUP to register):
http://www.xilinx.com/univ/uwkshp.htm
The Embedded Linux on MicroBlaze workshop will be
presented by Dr. John Williams, owner and CEO of PetaLogix, who architected the
original port of the Linux operating system to the Xilinx MicroBlaze processor
while at The University of Queensland, Australia. This is a unique opportunity
to interact with and learn from an expert in embedded Linux for Xilinx FPGAs.
Save the Date:
An additional Xilinx Professor Workshop is being
planned for May 27-28, 2010 at University of Alberta. Details, including course
topic, are to be determined.
CMC
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